Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
Presently, a final logic design (referenced herein as the top-level design) for a PLD may include many logic pieces (referenced herein as modules). All of the logic pieces may be implemented at one time to form a full implementation for the target PLD. Alternatively, each module may be designed and implemented separately. Implemented modules are then combined to form a full implementation for the target PLD. Some PLDs are configured to support dynamic reconfiguration while active. That is, some PLDs have the ability to reprogram a portion of the PLD while the rest of the PLD continues to operate normally. Since a portion of the device may be reconfigured while the device is active, some type of predefined macros or other entity must be used as interfaces to the reconfigurable modules. One such instantiation of this implementation uses three-state buffer (tbuf) macros (also referred to as bus macros) as the interfaces of the reconfigurable modules. During reconfiguration, the tbuf macros allow a given module to be isolated from the portion of the design that is not being reconfigured.
To implement a partial reconfiguration design successfully, a designer must follow a strict design methodology using disparate tools. Accordingly, there exists a need in the art for a single environment for implementing a partial reconfiguration circuit design for a PLD.